tic216a, tic216b, tic216d, tic216m, tic216n, tic216s 30/10/2012 comset semiconductors 1 | 3 semiconductors silicon triacs ? 6 a rms ? glass passivated wafer ? 100 v to 800 v off-state voltage ? max i gt of 5 ma (quadrants 1-3) ? sensitive gate triacs ? compliance to roh absolute maximum ratings symbol ratings value unit a b d m s n v drm repetitive peak off-state voltage (see note1) 100 200 400 600 700 800 v i t(rms) full-cycle rms on-state current at (or below) 70c case temperature (see note2) 6 a i tsm peak on-state surge current full-sine-wave (see note3) 60 a i tsm peak on-state surge current half-sine-wave (see note4) 70 a i gm peak gate current 1 a p gm peak gate power dissipation at (or below) 85c case temperature (pulse width 200 s) 2.2 w p g(av) average gate power dissipation at (or below) 85c case (see note5) 0.9 w t c operating case temperature range -40 to +110 c t st g storage temperature range -40 to +125 c t l lead temperature 1.6 mm from case for 10 seconds 230 c thermal characteristics symbol ratings value unit r ? jc junction to case thermal resistance 2.5 c/w r ? ja junction to free air thermal resistance 62.5
tic216a, tic216b, tic216d, tic216m, tic216n, tic216s 30/10/2012 comset semiconductors 2 | 3 semiconductors electrical characteristics tc=25c unless otherwise noted symbol ratings test condition(s) min typ max unit i drm repetitive peak off-state current v d = rated v drm , , i g = 0 t c = 110c - - 2 ma i gt gate trigger current v su pp l y = +12 v?, r l = 10 ? t p(g) = > 20 s - - 5 ma v su pp l y = +12 v?, r l = 10 ? t p(g) = > 20 s - - -5 v su pp l y = -12 v?, r l = 10 ? t p(g) = > 20 s - - -5 v su pp l y = -12 v?, r l = 10 ? t p(g) = > 20 s - - 10 v gt gate trigger voltage v su pp l y = +12 v?, r l = 10 ? t p(g) = > 20 s - - 2.2 v v su pp l y = +12 v?, r l = 10 ? t p(g) = > 20 s - - -2.2 v su pp l y = -12 v?, r l = 10 ? t p(g) = > 20 s - - -2.2 v su pp l y = -12 v?, r l = 10 ? t p(g) = > 20 s - - 3 i h holding current v supply = +12 v?, i g = 0 initiating i tm = 100 ma - - 30 ma v supply = -12 v?, i g = 0 initiating i tm = -100 ma - - -30 i l latching current v su pp l y = +12 v? (seenote7) - 50 - ma v su pp l y = -12 v? (seenote7) - -20 - v tm peak on-state voltage i tm = 8.4 a, i g = 50 ma (see note6) - - 1.7 v dv/dt critical rate of rise of off-state voltage v drm = rated v drm , i g = 0 t c = 110c - 50 - v/s dv/dt ? critical rise of communication voltage v drm = rated v drm , i trm = 8.4a t c = 70c 5 - - ? all voltages are whit respect to main terminal 1. notes: 1. these values apply bidirectionally for any va lue of resistance between the gate and main terminal 1. 2. this value applies for 50-hz full-sine-wave operat ion with resistive load. above 70c derate linearly to 110c case temperature at the rate of 150 ma/c. 3. this value applies for one 50-hz full-sine-wave when the device is operating at (or below) the rated value of on-state current. surge may be repeated a fter the device has returned to original thermal equilibrium. during the surge, gate control may be lost. 4. this value applies for one 50-hz half-sine-wave wh en the device is operating at (or below) the rated value of on-state current. surge may be repeated a fter the device has returned to original thermal equilibrium. during the surge, gate control may be lost. 5. this value applies for a maximum averaging time of 20 ms. 6. this parameters must be measured using pulse techniques, t w = 1s, duty cycle 2 %, voltage- sensing contacts, separate from the courr ent-carrying contacts are located within 3.2mm (1/8 inch) from de device body. 7. the triacs are triggered by a 15-v (open circui t amplitude) pulse supplied by a generator with the following characteristics : r g = 100 ? , t p(g) = 20 s, t r = 15ns, f = 1 khz.
tic216a, tic216b, tic216d, tic216m, tic216n, tic216s 30/10/2012 comset semiconductors 3 | 3 semiconductors mechanical data case to-220 revised september 2012 ????????? ? information furnished is believed to be accurate and reliable. ho wever, comset semiconductors assumes no responsibility for the consequences of use of such information nor for any infringement of patents or ot her rights of third parties which may results from its use. da ta are subject to change without notice. co mset semiconductors makes no warranty, representation or guarantee re garding the suitability of its products for any particular purpose, nor does comset semicond uctors assume any liability aris ing out of the application or us e of any product and specifica lly disclaims any and all liability, including without limitation consequential or in cidental damages. comset semiconductors? products are not au thorized for use as critical components in life support devices or systems. ? ? www.comsetsemi.com info@comsetsemi.com pin 1 : main terminal 1 pin 2 : main terminal 2 pin 3 : gate
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